J
jianhuachews
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Hi lahko kdorkoli zagotovi me VHDL kode za delimo s 50 vezje frekvenco divider z flip-flops? Hvala v adv.
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Wats up mr. slepar ... @ Jianhuachews: Tukaj je koda (synthesizable): [url = http://www.vhdlcodes.com/2010/08/vhdl-code-for-clock-divider.html] All About VHDL kode, PCB Oblikovanje in AVR: VHDL koda za Divider Clock [/url]Tukaj je koda: [url = http://vhdlguru.blogspot.com/2011/03/clock-frequency-converter-in-vhdl.html] VHDL kodiranje nasveti in triki: Clock Frequency pretvornik v VHDL [/url]
if (CNT = 1) potem CNT
if (rising_edge (Clk)) potem, če (števec <divide/2-1) potem števec
knjižnica IEEE; uporabo IEEE.std_logic_1164.all, uporaba IEEE.numeric_std.all, subjekt lab3C je vrata (Clk, nreset: v std_logic; output_clk: od std_logic; divide_value: v integer); end; arhitektura Vedenje lab3C je signal števec, deli: integer: = 0; začeli deliti