S
s3034585
Guest
halo guys jaz sem poskušal izvesti državni stroj v VHDL.jaz sem samo poskušam naložiti nekaj sprememb registrov in kasneje jih premik v kasnejših državah.
imam 4 določa, prosti tek, obremenitev, clk_st, izračunati.
v stanju i idle jih poskušati ponastaviti, v obremenitvi i obremenitev premik registrov z novimi vrednotami.v clk_st i premik država jih enkrat in izračun i izračunati vrednost, ki so jih xoring in jih nato premik.
problem, ki jaz sem sprednja stran je, da ko gre v stanje gibanja je premik registrov 2-krat.jaz sem nezmožen najti, zakaj ne Excute tem stanju 2-krat.
cany katera koli od prosim pomoč ...jaz sem pritrditev spodnjo kodo, ..
hvala vnaprej
-------------------------------------------------- ---------------------------------------------
arhitektura Vedenjska preskusa je
-------------------------------------------------- ----------------------------
signal C1, C2, C3: std_logic;Tip je State_Type (Idle, obremenitev, clk_st, izračunati);
signal Current_State, Next_State: State_Type;
-------------------------------------------------- ----------------------------
začeti
statereg: proces (CLK, Reset)
začeti
če Reset = '1 'potem
Current_State <= Idle;
elsif (clk'event in CLK = '1 '), potem
Current_State <= Next_State;
konca, če;
koncu postopka;proces (CLK, Current_State, reset)spremenljivka r1_r: std_logic_vector (18 downto 0);
spremenljivka r2_r: std_logic_vector (21 downto 0);
spremenljivka r3_r: std_logic_vector (22 downto 0);
spremenljivka empty_bit: std_logic;
spremenljivka CNT: integer;
spremenljivka cnt_test: integer;
spremenljivka ref_bit: std_logic_vector (64-1 downto 0);
spremenljivka shft_reg_r3: std_logic_vector (2 downto 0);
spremenljivka shft_reg_r3_1: std_logic_vector (1 downto 0);
spremenljivka shft_reg_r3_2: std_logic;
spremenljivka shft_reg_r3_3: std_logic_vector (2 downto 0);
začeti
primeru je Current_State
ko Idle =>
r1_r: = (drugi => '0 ');
r2_r: = (drugi => '0 ');
r3_r: = (drugi => '0 ');
CNT: = 0;
empty_bit: = '0 ';
FB1 <= 0 ";
FB2 <= 0 ";
fb3 <= 0 ";
c1 <= 0 ";
c2 <= 0 ";
c3 <= 0 ";
shft_reg_r3: = (drugi => '0 ');
shft_reg_r3_1: = (drugi => '0 ');
shft_reg_r3_2: = '0 ';
shft_reg_r3_3: = (drugi => '0 ');
ref_bit: = (drugi => '0 ');
cnt_test: = 0;
če obremenitev = '1 'potem
Next_State <= load_reg;
drugega
Next_State <= idle;
konca, če;
ko load_reg =>
Next_State <= clk_st;
ref_bit: = Reference;
r1_r: = Vector_In (63 downto 45);
r2_r: = Vector_In (44 downto 23);
empty_bit: = r1_r (1
<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Cool" border="0" />
XOR r2_r (21) XOR ref_bit (Ks_Width-1);
shft_reg_r3: = "00" & empty_bit - 22 bit
shft_reg_r3_1: = '0 '& r3_r (21), - 21 bit
shft_reg_r3_2: = r3_r (20), - 20 bit
shft_reg_r3_3: = "00" & r3_r (7), - 7 bit
CNT: = 1;
ko clk_st =>
Next_State <= izračun;
ref_bit (Ks_Width-1 downto 0): = ref_bit (Ks_Width-2 downto 0) in "0";
- "Da je ne moremo ref_bit 2 krat ... I dont vem, zakaj"
cnt_test: = cnt_test 1;
empty_bit: = r1_r (1
<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Cool" border="0" />
XOR r2_r (21) XOR ref_bit (Ks_Width-1);
shft_reg_r3: = shft_reg_r3 (1 downto 0) & empty_bit - 22 bit
shft_reg_r3_1: = shft_reg_r3_1 (0) & empty_bit - 21 bit
shft_reg_r3_3: = shft_reg_r3_3 (1 downto 0) & r3_r (7), - 7 bit
shft_reg_r3_2: = empty_bit; - 20 bit
c1 <= r1_r (
<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Cool" border="0" />
;
c2 <= r2_r (10);
c3 <= r3_r (10);
CNT: = 2;če izračun> =
Next_State <= izračun;
ref_bit (Ks_Width-1 downto 0): = ref_bit (Ks_Width-2 downto 0) in "0";
empty_bit: = r1_r (1
<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Cool" border="0" />
XOR r2_r (21) XOR ref_bit (Ks_Width-1);
if (C3 = C1) ali (c3 c2 =) in nato - 2
shft_reg_r3: = shft_reg_r3 (1 downto 0) & empty_bit - 22 bit
shft_reg_r3_1: = shft_reg_r3_1 (0) & empty_bit - 21 bit
shft_reg_r3_3: = shft_reg_r3_3 (1 downto 0) & r3_r (7), - 7 bit
shft_reg_r3_2: = empty_bit; - 20 bit
"Na eni particuar pod pogojem, da bo izhod ..."
ko drugi =>
null;
koncu postopka;
koncu postopka;
-------------------------------------------------- -----------------------------------------
imam 4 določa, prosti tek, obremenitev, clk_st, izračunati.
v stanju i idle jih poskušati ponastaviti, v obremenitvi i obremenitev premik registrov z novimi vrednotami.v clk_st i premik država jih enkrat in izračun i izračunati vrednost, ki so jih xoring in jih nato premik.
problem, ki jaz sem sprednja stran je, da ko gre v stanje gibanja je premik registrov 2-krat.jaz sem nezmožen najti, zakaj ne Excute tem stanju 2-krat.
cany katera koli od prosim pomoč ...jaz sem pritrditev spodnjo kodo, ..
hvala vnaprej
-------------------------------------------------- ---------------------------------------------
arhitektura Vedenjska preskusa je
-------------------------------------------------- ----------------------------
signal C1, C2, C3: std_logic;Tip je State_Type (Idle, obremenitev, clk_st, izračunati);
signal Current_State, Next_State: State_Type;
-------------------------------------------------- ----------------------------
začeti
statereg: proces (CLK, Reset)
začeti
če Reset = '1 'potem
Current_State <= Idle;
elsif (clk'event in CLK = '1 '), potem
Current_State <= Next_State;
konca, če;
koncu postopka;proces (CLK, Current_State, reset)spremenljivka r1_r: std_logic_vector (18 downto 0);
spremenljivka r2_r: std_logic_vector (21 downto 0);
spremenljivka r3_r: std_logic_vector (22 downto 0);
spremenljivka empty_bit: std_logic;
spremenljivka CNT: integer;
spremenljivka cnt_test: integer;
spremenljivka ref_bit: std_logic_vector (64-1 downto 0);
spremenljivka shft_reg_r3: std_logic_vector (2 downto 0);
spremenljivka shft_reg_r3_1: std_logic_vector (1 downto 0);
spremenljivka shft_reg_r3_2: std_logic;
spremenljivka shft_reg_r3_3: std_logic_vector (2 downto 0);
začeti
primeru je Current_State
ko Idle =>
r1_r: = (drugi => '0 ');
r2_r: = (drugi => '0 ');
r3_r: = (drugi => '0 ');
CNT: = 0;
empty_bit: = '0 ';
FB1 <= 0 ";
FB2 <= 0 ";
fb3 <= 0 ";
c1 <= 0 ";
c2 <= 0 ";
c3 <= 0 ";
shft_reg_r3: = (drugi => '0 ');
shft_reg_r3_1: = (drugi => '0 ');
shft_reg_r3_2: = '0 ';
shft_reg_r3_3: = (drugi => '0 ');
ref_bit: = (drugi => '0 ');
cnt_test: = 0;
če obremenitev = '1 'potem
Next_State <= load_reg;
drugega
Next_State <= idle;
konca, če;
ko load_reg =>
Next_State <= clk_st;
ref_bit: = Reference;
r1_r: = Vector_In (63 downto 45);
r2_r: = Vector_In (44 downto 23);
empty_bit: = r1_r (1
<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Cool" border="0" />
XOR r2_r (21) XOR ref_bit (Ks_Width-1);
shft_reg_r3: = "00" & empty_bit - 22 bit
shft_reg_r3_1: = '0 '& r3_r (21), - 21 bit
shft_reg_r3_2: = r3_r (20), - 20 bit
shft_reg_r3_3: = "00" & r3_r (7), - 7 bit
CNT: = 1;
ko clk_st =>
Next_State <= izračun;
ref_bit (Ks_Width-1 downto 0): = ref_bit (Ks_Width-2 downto 0) in "0";
- "Da je ne moremo ref_bit 2 krat ... I dont vem, zakaj"
cnt_test: = cnt_test 1;
empty_bit: = r1_r (1
<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Cool" border="0" />
XOR r2_r (21) XOR ref_bit (Ks_Width-1);
shft_reg_r3: = shft_reg_r3 (1 downto 0) & empty_bit - 22 bit
shft_reg_r3_1: = shft_reg_r3_1 (0) & empty_bit - 21 bit
shft_reg_r3_3: = shft_reg_r3_3 (1 downto 0) & r3_r (7), - 7 bit
shft_reg_r3_2: = empty_bit; - 20 bit
c1 <= r1_r (
<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Cool" border="0" />
;
c2 <= r2_r (10);
c3 <= r3_r (10);
CNT: = 2;če izračun> =
Next_State <= izračun;
ref_bit (Ks_Width-1 downto 0): = ref_bit (Ks_Width-2 downto 0) in "0";
empty_bit: = r1_r (1
<img src="http://www.edaboard.com/images/smiles/icon_cool.gif" alt="Cool" border="0" />
XOR r2_r (21) XOR ref_bit (Ks_Width-1);
if (C3 = C1) ali (c3 c2 =) in nato - 2
shft_reg_r3: = shft_reg_r3 (1 downto 0) & empty_bit - 22 bit
shft_reg_r3_1: = shft_reg_r3_1 (0) & empty_bit - 21 bit
shft_reg_r3_3: = shft_reg_r3_3 (1 downto 0) & r3_r (7), - 7 bit
shft_reg_r3_2: = empty_bit; - 20 bit
"Na eni particuar pod pogojem, da bo izhod ..."
ko drugi =>
null;
koncu postopka;
koncu postopka;
-------------------------------------------------- -----------------------------------------