in kako to storiti? lahko uporabim hspice da simulira moj design uporabo. SPEF datoteko? [Quote = au_sun] u lahko uporabite za Timing anaylsis in navzkrižno govori anlysis [/quote]
hi oblikovalec, moja 2 centa, 1. Si prebral preusmerjeni netlist in SPEF datoteko v primetime in opravljajo post-preusmerjen analiza časa. 2. Si prebral preusmerjeni netlist in SPEF datoteko in ustvarjajo SDF [Standard Delay format] file. Uporabite preusmerjen netlist in SDF datotek za vrata ravni simulacijo, da preverite, ali ste srečanje funkcionalnost in čas. Hvalite Gospoda. Lep pozdrav, vlsichipdesigner http://www.vlsichipdesign.com chip design, ki Eazy
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.