RAM / FF inferrention v ISE.

[jsiiiii]

Jaz delam z Verilog in uporabo ISE Compiler.Moj problem je RAM inferrention za signal.ISE je impementing moj signal v FF in ne vem zakaj.Koda:
Koda:reg [31:0] ct_tab_start_next_n [7:0];Vedno @ (posedgeCLK)

if (ag_start) ct_tab_start_next_n [ct_dev_num] <= ag_secend_n;

drugje, če (ag_go_to_next_block_addr) ct_tab_start_next_n [ct_dev_num] <= ag_start_block_n_addr;

drugje, če (ag_go_to_next_block_n) ct_tab_start_next_n [ct_dev_num] <= ag_next_n;

drugje, če (ag_go_to_next_block_m) ct_tab_start_next_n [ct_dev_num] <= ag_next_m;