Potrebujete pomoč za povezovanje z FPGA SDRAM (MT48LC8M16A2)

M

myfpga007

Guest
Hi all,

Jaz sem v stiku z FPGA spartan3 spomin MT48LC8M16A2 SDRAM.Včasih sem testbench in spomin model na voljo na spletni Micron, za katere deluje v redu.Vendar pa se spremeni testbench, da bi bilo synthesizable in test na strojni opremi ne deluje.Kljub temu, da je še zmeraj dela na simulatorju.

Vprašanje je, med brati operacijo sem vedno dobil iste podatke X "0007"
Lahko kdorkoli pomoč mi najti vprašanje.Tukaj je spremenjen kodeks testbench:knjižnica IEEE;
uporaba ieee.std_logic_1164.all;
uporaba ieee.numeric_std.all;uporaba IEEE.STD_LOGIC_arith.all;
uporaba IEEE.STD_LOGIC_unsigned.all;

ENOTI tb_synthesizable IS
Generični (
addr_bits: Teorija: = 12;
data_bits: Teorija: = 16);
PORT (
dip: IN STD_LOGIC_VECTOR (7 downto 0), - določiti pomnilnik (temp_buf) kraj, ki se glasi
ledout: OUT STD_LOGIC_VECTOR (15 downto 0), - 16 bit podatkov iz pomnilnika (temp_buf)
Dq: INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0);
Addr: OUT STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Ba: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
sdram_clk: OUT std_logic;
CLK: IN std_logic; - 100 MHz zunanje CLK
Čke: OUT std_logic;
Cs_n: OUT std_logic;
Cas_n: OUT std_logic;
Ras_n: OUT std_logic;
We_n: OUT std_logic;
Dqm: OUT STD_LOGIC_VECTOR (1 DOWNTO 0));

END tb_synthesizable;

ARHITEKTURA test tb_synthesizable IS
- Nenehno TCK: TIME: = 10 ns;
- Nenehno addr_bits: Teorija: = 12;
- Nenehno data_bits: Teorija: = 16;

- KOMPONENTA mt48lc8m16a2
- PORT (
-
- Dq: INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0), -: = (Ostalo => 'Z');
--Naslov: IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0), -: = (Ostalo => '0 ');
- Ba: IN STD_LOGIC_VECTOR (1 DOWNTO 0), -: = "00";
- CLK: IN std_logic; -: = '0 ';
- Čke: IN std_logic; -: = '0 ';
- Cs_n: IN std_logic; -: = '1 ';
- Cas_n: IN std_logic; -: = '0 ';
- Ras_n: IN std_logic; -: = '0 ';
- We_n: IN std_logic; -: = '0 ';
- Dqm: IN STD_LOGIC_VECTOR (1 DOWNTO 0) -: = "00"
-);
- END komponente;

- ZA VSE: mt48lc8m16a2 UPORABA ENOTI work.mt48lc8m16a2 (obnašajo);

- SIGNAL PDQ: STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0), - se PDQ nadomesti z Dq
SIGNAL pAddr: STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
SIGNAL PBA: STD_LOGIC_VECTOR (1 DOWNTO 0);
- SIGNAL pClk: std_logic;
SIGNAL pCke: std_logic;
SIGNAL pCs_n: std_logic;
SIGNAL pCas_n: std_logic;
SIGNAL pRas_n: std_logic;
SIGNAL pWe_n: std_logic;
SIGNAL pDqm: STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL stim_done: boolean: = false;
SIGNAL clk_done: boolean: = false;-------------------------------- MY SIGNALI ---------------- -------------------------------
SIGNAL count: Teorija: = 0; - kolesarjenja po različnih državah (ki zahtevajo postopki)
Tip je mem array (0 do 14) z dne std_logic_vector (15 downto 0), - za shranjevanje podatkov brati iz SDRAM
signal temp_buf: MEM;
BEGIN
- U1: mt48lc8m16a2
- PORT MAP (
- Dq = Dq>
- Addr => pAddr,
- Ba => PBA,
- - CLK => pClk,
- CLK => sdram_clk1,
- Čke => pCke,
- Cs_n => pCs_n,
- Ras_n => pRas_n,
- Cas_n => pCas_n,
- We_n => pWe_n,
- Dqm => pDqm
-);
-
- Dq <= PDQ;
Addr <= pAddr;
Ba <= PBA;
Čke <= pCke;
Cs_n <= pCs_n;
Cas_n <= pCas_n;
Ras_n <= pRas_n;
We_n <= pWe_n;
Dqm <= pDqm;
sdram_clk <= CLK;

ledout <= temp_buf (conv_integer (dip));
- Ledout <= temp_buf (2), ko (dip = "00000010") drug (drugi => 'Z');
- Ledout <= temp_buf (3), ko (dip = "00000011") drug (drugi => 'Z');
- Ledout <= temp_buf (4), ko (dip = "00000100") drug (drugi => 'Z');
- Ledout <= temp_buf (5), ko (dip = "00000101") drug (drugi => 'Z');
- Ledout <= temp_buf (6), ko (dip = "00000110") drug (drugi => 'Z');
- Ledout <= temp_buf (7), ko (dip = "00000111") drug (drugi => 'Z');

stimulator: PROCES (CLK, COUNT)
POSTOPEK ACTIVE (Ba_in: STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in: STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in: STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1 ';
pCs_n <= 0 ";
pRas_n <= 0 ";
pCas_n <= '1 ';
pWe_n <= '1 ';
pDqm <= "00";
PBA <= Ba_in;
pAddr <= Addr_in;
Dq <= Dq_in;
- Počakajte TCK;
END;

POSTOPEK AUTO_REFRESH IS
BEGIN
pCke <= '1 ';
pCs_n <= 0 ";
pRas_n <= 0 ";
pCas_n <= 0 ";
pWe_n <= '1 ';
pDqm <= "00";
- PBA <= "00";
- PAddr <= (Ostalo => '0 ');
Dq <= (Ostalo => 'Z');
- Počakajte TCK;
END;

POSTOPEK BURST_TERM IS
BEGIN
pCke <= '1 ';
pCs_n <= 0 ";
pRas_n <= '1 ';
pCas_n <= '1 ';
pWe_n <= 0 ";
pDqm <= "00";
- PBA <= "00";
- PAddr <= (Ostalo => '0 ');
Dq <= (Ostalo => 'Z');
- Počakajte TCK;
END;

POSTOPEK LOAD_MODE_REG (Ba_in: STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in: STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1 ';
pCs_n <= 0 ";
pRas_n <= 0 ";
pCas_n <= 0 ";
pWe_n <= 0 ";
pDqm <= "00";
PBA <= Ba_in;
pAddr <= Addr_in;
Dq <= (Ostalo => 'Z');
- Počakajte TCK;
END;

POSTOPEK NOP (Dq_in: STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1 ';
pCs_n <= 0 ";
pRas_n <= '1 ';
pCas_n <= '1 ';
pWe_n <= '1 ';
pDqm <= "00";
- PBA <= "00";
- PAddr <= (Ostalo => '0 ');
Dq <= Dq_in;
- Počakajte TCK;
END;

POSTOPEK PRECHARGE (Ba_in: STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in: STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in: STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1 ';
pCs_n <= 0 ";
pRas_n <= 0 ";
pCas_n <= '1 ';
pWe_n <= 0 ";
pDqm <= "00";
PBA <= Ba_in;
pAddr <= Addr_in;
Dq <= Dq_in;
- Počakajte TCK;
END;

POSTOPEK READ (Ba_in: STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in: STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in: STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1 ';
pCs_n <= 0 ";
pRas_n <= '1 ';
pCas_n <= 0 ";
pWe_n <= '1 ';
pDqm <= "00";
PBA <= Ba_in;
pAddr <= Addr_in;
Dq <= Dq_in;
- Počakajte TCK;
END;

- Pisanje
POSTOPEK NAPIŠI (Ba_in: STD_LOGIC_VECTOR (1 DOWNTO 0);
Addr_in: STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0);
Dq_in: STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0)) IS
BEGIN
pCke <= '1 ';
pCs_n <= 0 ";
pRas_n <= '1 ';
pCas_n <= 0 ";
pWe_n <= 0 ";
pDqm <= "00";
PBA <= Ba_in;
pAddr <= Addr_in;
Dq <= Dq_in;
- Počakajte TCK;
END;

BEGIN

if (rising_edge (CLK) in število <60) pa

count <= count 1, - count izvaja različnih držav

primeru je število

če 0 =>
Dq <= (Ostalo => 'Z');
pAddr <= (Ostalo => '0 ');
PBA <= "00";
- PClk <= 0 ";
pCke <= 0 ";
pCs_n <= '1 ';
pCas_n <= 0 ";
pRas_n <= 0 ";
pWe_n <= 0 ";
pDqm <= "00";
temp_buf (0) <= X "0000";

- UKAZ BA-naslov DQ
ko 1 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 2 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 3 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 4 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 5 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 6 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 7 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 8 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 9 =>
NOP ("ZZZZZZZZZZZZZZZZ");
če 10 =>
NOP ("ZZZZZZZZZZZZZZZZ");

- Potrebujemo 100 nas moč up zaporedje.I uporabo 10 NOPs tukaj kot zahteva primer.
, ko je 11 =>
PRECHARGE ("00", "010000000000", "ZZZZZZZZZZZZZZZZ");
ko 12 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 13 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 14 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 15 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 16 =>
AUTO_REFRESH;

ko 17 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 18 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko je 19 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 20 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 21 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 22 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 23 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 24 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 25 =>
AUTO_REFRESH;

ko 26 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 27 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 28 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 29 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 30 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 31 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 32 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 33 =>
LOAD_MODE_REG ("00", "000000110011");
ko 34 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 35 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 36 =>
ACTIVE ("00", "000000000000", "ZZZZZZZZZZZZZZZZ");
ko 37 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 38 =>
Write ("00", "000000000000", "0000000000000000"); - "010000000000"
ko 39 =>
NOP ("0000000000000001");
ko 40 =>
ACTIVE ("01", "000000000000", "0000000000000010");
ko 41 =>
NOP ("0000000000000011");
ko 42 =>
NOP ("0000000000000100");
ko 43 =>
NOP ("0000000000000101");
ko 44 =>
NOP ("0000000000000110");
ko 45 =>
NOP ("0000000000000111");ko 46 =>
READ ("00", "010000000000", "ZZZZZZZZZZZZZZZZ");
temp_buf (1) <= dq;
ko 47 =>
NOP ("ZZZZZZZZZZZZZZZZ");
temp_buf (2) <= dq;
ko 48 =>
ACTIVE ("01", "000000000000", "ZZZZZZZZZZZZZZZZ");
temp_buf (3) <= dq;
ko 49 =>
NOP ("ZZZZZZZZZZZZZZZZ");
temp_buf (4) <= dq;
ko 50 =>
NOP ("ZZZZZZZZZZZZZZZZ");
temp_buf (5) <= dq;

ko 51 =>
NOP ("ZZZZZZZZZZZZZZZZ");
temp_buf (6) <= dq;
ko 52 =>
NOP ("ZZZZZZZZZZZZZZZZ");
temp_buf (7) <= dq;
ko 53 =>
NOP ("ZZZZZZZZZZZZZZZZ");ko 54 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 55 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 56 =>
NOP ("ZZZZZZZZZZZZZZZZ");
ko 57 =>

ko drugi =>
null;

END CASE;
- Uveljaviti lažne
- Poročilo Konec Spodbujanje Zaznana je! "
- Severity opomba;
- Stim_done <= true;
- Čakanja;

END IF;
END procesa;

- Ura: PROCES
- Variabilni done_time: čas;
- BEGIN
- Pclk <= 0 ";
- Počakajte, TCK / 2;
- Čeprav ne stim_done zanke
- Pclk <= '1 ';
- Počakajte, TCK / 2;
- Pclk <= 0 ";
- Počakajte, TCK / 2;
- END LOOP;
- Done_time: = zdaj TCK;
- Medtem ko se zdaj <done_time LOOP - ena zadnjih ure, da konča zadnji ukaz
- Pclk <= '1 ';
- Počakajte, TCK / 2;
- Pclk <= 0 ";
- Počakajte, TCK / 2;
- END LOOP;
- Uveljaviti lažne
- Poročilo Obešeni ure dejavnost "
- Severity opomba;
- Clk_done <= true;
- Čakanja;
- END procesa;
END test;

Hvala vnaprej

Koda:

 
Če prav razumem, da je testbench, ki jih Micron za namene preverjanja, kajne?Kot v ne za namen sinteze.Če je temu tako, potem jaz ne bi bil presenečen, če ne to, kar hočeš, ko sintetizirali.

Kot vmesnik za SDRAM spartan3 boste potrebovali nekaj upravljavca IP SDRAM iz Xilinx, ali mestih, kot so opencores .

Upam, da pomaga.

 
Svoj šele včasih lažje porabi nekaj časa obravnave list in pisanje lastnih kodo.

Njena grobi ampak res

 
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