C
cutepotato
Guest
To je kratko kodo, napisano v VHDL je potekal v Active-HDL.
ga pripravlja uspešno, vendar rezultatov simulacije narobe.
ram, da se zdi, da ne dela kot jaz ne morem dobiti vrednost iz RAM-a.
plz bi si jih pogledamo?Hvala lepa!
----- 2D FDM
library IEEE;
uporaba IEEE.STD_LOGIC_1164.ALL;
uporaba IEEE.STD_LOGIC_ARITH.ALL;
uporaba IEEE.STD_LOGIC_UNSIGNED.ALL;
uporaba IEEE.numeric_std.all;Podjetje je twoDfdm
pristanišča (CLK: v std_logic;
en: v std_logic; - omogoči celotno vezje, da bo delo, ko "1"
din: v std_logic_vector (15 downto 0);
reset: in std_logic;
wr: v std_logic;
dout: od std_logic_vector (15 downto 0));
end twoDfdm;architecture Behavioral of twoDfdm je
- tip my_array je array (0 do 255) za std_logic_vector (15 downto 0);
--
- signal u: my_array;
- signal v: my_array;signal addr1: integer območju od 0 do 15;
signal addr2: integer območju od 0 do 15;
signal naslov: integer razponu od 0 do 255;
signal address_up: integer razponu od 0 do 255;
signal address_down: integer razponu od 0 do 255;
signal address_right: integer razponu od 0 do 255;
signal address_left: integer razponu od 0 do 255;
signal data1: std_logic_vector (15 downto 0);
signal data2: std_logic_vector (15 downto 0);
signal data3: std_logic_vector (15 downto 0);
signal data4: std_logic_vector (15 downto 0);
signal data5: std_logic_vector (15 downto 0);
signal data0: std_logic_vector (15 downto 0);
signal data9: std_logic_vector (17 downto 0);
signal znak: std_logic_vector (11 downto 0);
signal comp: std_logic;
signal en_delay: std_logic;
signal WE: std_logic: = '0 ';
signal OE: std_logic: = '0 ';
komponenta je ram
pristanišče (Naslov: INTEGER v razponu od 0 do 255;
CLK: v std_logic;
Podatki: InOut std_logic_vector (15 downto 0);
CS, WE, OE: v std_logic);
end komponente ram;
začeti- Pomnilnik 16 * 16
postopku (reset, CLK) je
- spremenljivka a1: integer območju od 0 do 15;
- Spremenljivka a2: integer območju od 0 do 15;
začeti
if (reset = '0 ') then
addr1 <= 0;
addr2 <= 0;
elsif rising_edge (CLK) potem
if (addr2 = 13) then
addr1 <= 0;
addr2 <= 0;
elsif addr1 = 13 potem
addr1 <= 0;
addr2 <= addr2 1;
elsif en = '1 'then
addr1 <= addr1 1;
- end if;
end if;
end if;
koncu postopka;
- naslov
set_addr: proces (addr1, addr2) je
začeti
- WE <= '1 ';
naslov <= addr1 1 (addr2 1) * 16 po 5ns;
koncu procesa set_addr;
- Lut 1 * 4
Lut: proces (addr1, addr2) je
začeti
address_up <addr1 = 1 addr2 * 16 po 5ns;
address_down <= addr1 1 (addr2 2) * 16 po 5ns;
address_right <= addr1 2 (addr2 1) * 16 po 5ns;
address_left <= addr1 (addr2 1) * 16 po 5ns;
koncu procesa lut;g1: ram vrata map (Address => address_up, CLK => CLK, data => data1, CS => en, WE => WE, OE => OE);
g2: ram vrata map (Address => address_down, CLK => CLK, data => data2, CS => en, WE => WE, OE => OE);
G3: ram vrata map (Address => address_right, CLK => CLK, data => data3, CS => en, WE => WE, OE => OE);
G4: ram vrata map (Address => address_left, CLK => CLK, data => data4, CS => en, WE => WE, OE => OE);
g5: ram vrata map (Address => naslov, CLK => CLK, data => data5, CS => en, WE => WE, OE => OE);
- seštevalnik
izračun: proces (CLK, data1, data2, data3, data4) je
začeti
če reset = '0 'then
data9 <= (drugi => '0 ');
elsif rising_edge (CLK) potem
data9 <= ( "00" & data1) ( "00" & data2) ( "00" & data3) ( "00" & data4);
end if;
koncu procesa izračun;- u vnos podatkov
- caculate končno vrednost razlike
set_array: proces (reset, CLK) je
začeti
če reset = '0 'then
data1 <= (drugi => '0 ');
data2 <= (drugi => '0 ');
data3 <= (drugi => '0 ');
data4 <= (drugi => '0 ');
data5 <= (drugi => '0 ');
elsif rising_edge (CLK) potem
if (comp = "1" in en = '1 ') then
OE <= '0 ';
WE <= '1 ';
elsif (comp = '0 'in en = '1') then
OE <= '1 ';
WE <= '0 ';
end if;
end if;
koncu procesa set_array;- Presoditi, ali nova vrednost je enaka prvotni vrednosti
proces (data9, data5, en, CLK) je
začeti
če (en = '0 ') then
znak <= (drugi => '1 ');
elsif rising_edge (CLK) potem
znak <= data5 (15 downto 4) XOR data9 (17 downto 6);
end if;
koncu postopka;
- Nemudoma po en uro, s katero bi signal comp
omogočiti: proces (reset, CLK) je
začeti
if (reset = '0 ') then
en_delay <= '0 ';
elsif rising_edge (CLK) potem
en_delay <= en;
end if;
koncu procesa omogočajo;
- Rezultat primerjave output signal comp
primerjavo: proces (en_delay, znak) je
začeti
če en_delay = '0 'then
comp <= '1 ';
elsif znak = "000000000000" in nato
comp <= '0 ';
še
comp <= '1 ';
end if;
koncu procesa primerjati;- Proizvodnja končnih podatkov, kadar operacija konča
output: proces (reset, CLK) je
začeti
če reset = '0 'then
dout <= (drugi => '0 ');
elsif rising_edge (CLK) potem
if (comp = '0 'in en = '1') then
- WE <= '0 ';
- OE <= '1 ';
data0 <= data9 (17 downto 2), po 5ns;
dout <= data0;
še
dout <= (drugi => '0 ');
end if;
end if;
konec postopka proizvodnje;
g: ram vrata map (Address => naslov, CLK => CLK, data => data0, CS => en, WE => WE, OE => OE);
end Behavioral;
-------- to je oven
library IEEE;
uporaba IEEE.std_logic_1164.all;
uporaba IEEE.std_logic_unsigned.all;
- ram256x16
Podjetje je ram
pristanišče (Naslov: INTEGER v razponu od 0 do 255;
Podatki: InOut std_logic_vector (15 downto 0);
CS, WE, OE: v std_logic;
CLK: v std_logic
);
Zato podjetje ram;
arhitektura RTL of ram je
Tip ram_array je array (0 do 255) za std_logic_vector (15 downto 0);
signal mem: ram_array;začeti
- P0: proces (CS, WE, OE, Data) je
- tip ram_array je array (0 do 255) za std_logic_vector (15 downto 0);
- spremenljivka mem: ram_array;
set_array: proces (CS, CLK) jekonstanta prog: ram_array: = (
16 => "1000000000000000", 32 => "1000000000000000", 48 => "1000000000000000", 64 => "1000000000000000", 80 => "1000000000000000", 96 => "1000000000000000"
112 => "1000000000000000", 128 => "1000000000000000", 144 => "1000000000000000", 160 => "1000000000000000", 176 => "1000000000000000", 192 => "1000000000000000"
208 => "1000000000000000", 224 => "1000000000000000", 240 => "1000000000000000", drugi => (drugi => '0 '));
začeti
če CS = '0 'then
če falling_edge (CLK) potem
mem <= prog;
end if;
end if;
koncu procesa set_array;read_mem: proces (naslov, OE)
začeti
če OE = '0 'then
Podatki <= mem (naslov);
še
Podatki <= (drugi => 'Z');
end if;
koncu procesa read_mem;
write_mem: proces (naslov, WE)
začeti
če WE = '0 'then
mem (Naslov) <= data;
end if;
koncu procesa write_mem;end architecture RTL;
ga pripravlja uspešno, vendar rezultatov simulacije narobe.
ram, da se zdi, da ne dela kot jaz ne morem dobiti vrednost iz RAM-a.
plz bi si jih pogledamo?Hvala lepa!
----- 2D FDM
library IEEE;
uporaba IEEE.STD_LOGIC_1164.ALL;
uporaba IEEE.STD_LOGIC_ARITH.ALL;
uporaba IEEE.STD_LOGIC_UNSIGNED.ALL;
uporaba IEEE.numeric_std.all;Podjetje je twoDfdm
pristanišča (CLK: v std_logic;
en: v std_logic; - omogoči celotno vezje, da bo delo, ko "1"
din: v std_logic_vector (15 downto 0);
reset: in std_logic;
wr: v std_logic;
dout: od std_logic_vector (15 downto 0));
end twoDfdm;architecture Behavioral of twoDfdm je
- tip my_array je array (0 do 255) za std_logic_vector (15 downto 0);
--
- signal u: my_array;
- signal v: my_array;signal addr1: integer območju od 0 do 15;
signal addr2: integer območju od 0 do 15;
signal naslov: integer razponu od 0 do 255;
signal address_up: integer razponu od 0 do 255;
signal address_down: integer razponu od 0 do 255;
signal address_right: integer razponu od 0 do 255;
signal address_left: integer razponu od 0 do 255;
signal data1: std_logic_vector (15 downto 0);
signal data2: std_logic_vector (15 downto 0);
signal data3: std_logic_vector (15 downto 0);
signal data4: std_logic_vector (15 downto 0);
signal data5: std_logic_vector (15 downto 0);
signal data0: std_logic_vector (15 downto 0);
signal data9: std_logic_vector (17 downto 0);
signal znak: std_logic_vector (11 downto 0);
signal comp: std_logic;
signal en_delay: std_logic;
signal WE: std_logic: = '0 ';
signal OE: std_logic: = '0 ';
komponenta je ram
pristanišče (Naslov: INTEGER v razponu od 0 do 255;
CLK: v std_logic;
Podatki: InOut std_logic_vector (15 downto 0);
CS, WE, OE: v std_logic);
end komponente ram;
začeti- Pomnilnik 16 * 16
postopku (reset, CLK) je
- spremenljivka a1: integer območju od 0 do 15;
- Spremenljivka a2: integer območju od 0 do 15;
začeti
if (reset = '0 ') then
addr1 <= 0;
addr2 <= 0;
elsif rising_edge (CLK) potem
if (addr2 = 13) then
addr1 <= 0;
addr2 <= 0;
elsif addr1 = 13 potem
addr1 <= 0;
addr2 <= addr2 1;
elsif en = '1 'then
addr1 <= addr1 1;
- end if;
end if;
end if;
koncu postopka;
- naslov
set_addr: proces (addr1, addr2) je
začeti
- WE <= '1 ';
naslov <= addr1 1 (addr2 1) * 16 po 5ns;
koncu procesa set_addr;
- Lut 1 * 4
Lut: proces (addr1, addr2) je
začeti
address_up <addr1 = 1 addr2 * 16 po 5ns;
address_down <= addr1 1 (addr2 2) * 16 po 5ns;
address_right <= addr1 2 (addr2 1) * 16 po 5ns;
address_left <= addr1 (addr2 1) * 16 po 5ns;
koncu procesa lut;g1: ram vrata map (Address => address_up, CLK => CLK, data => data1, CS => en, WE => WE, OE => OE);
g2: ram vrata map (Address => address_down, CLK => CLK, data => data2, CS => en, WE => WE, OE => OE);
G3: ram vrata map (Address => address_right, CLK => CLK, data => data3, CS => en, WE => WE, OE => OE);
G4: ram vrata map (Address => address_left, CLK => CLK, data => data4, CS => en, WE => WE, OE => OE);
g5: ram vrata map (Address => naslov, CLK => CLK, data => data5, CS => en, WE => WE, OE => OE);
- seštevalnik
izračun: proces (CLK, data1, data2, data3, data4) je
začeti
če reset = '0 'then
data9 <= (drugi => '0 ');
elsif rising_edge (CLK) potem
data9 <= ( "00" & data1) ( "00" & data2) ( "00" & data3) ( "00" & data4);
end if;
koncu procesa izračun;- u vnos podatkov
- caculate končno vrednost razlike
set_array: proces (reset, CLK) je
začeti
če reset = '0 'then
data1 <= (drugi => '0 ');
data2 <= (drugi => '0 ');
data3 <= (drugi => '0 ');
data4 <= (drugi => '0 ');
data5 <= (drugi => '0 ');
elsif rising_edge (CLK) potem
if (comp = "1" in en = '1 ') then
OE <= '0 ';
WE <= '1 ';
elsif (comp = '0 'in en = '1') then
OE <= '1 ';
WE <= '0 ';
end if;
end if;
koncu procesa set_array;- Presoditi, ali nova vrednost je enaka prvotni vrednosti
proces (data9, data5, en, CLK) je
začeti
če (en = '0 ') then
znak <= (drugi => '1 ');
elsif rising_edge (CLK) potem
znak <= data5 (15 downto 4) XOR data9 (17 downto 6);
end if;
koncu postopka;
- Nemudoma po en uro, s katero bi signal comp
omogočiti: proces (reset, CLK) je
začeti
if (reset = '0 ') then
en_delay <= '0 ';
elsif rising_edge (CLK) potem
en_delay <= en;
end if;
koncu procesa omogočajo;
- Rezultat primerjave output signal comp
primerjavo: proces (en_delay, znak) je
začeti
če en_delay = '0 'then
comp <= '1 ';
elsif znak = "000000000000" in nato
comp <= '0 ';
še
comp <= '1 ';
end if;
koncu procesa primerjati;- Proizvodnja končnih podatkov, kadar operacija konča
output: proces (reset, CLK) je
začeti
če reset = '0 'then
dout <= (drugi => '0 ');
elsif rising_edge (CLK) potem
if (comp = '0 'in en = '1') then
- WE <= '0 ';
- OE <= '1 ';
data0 <= data9 (17 downto 2), po 5ns;
dout <= data0;
še
dout <= (drugi => '0 ');
end if;
end if;
konec postopka proizvodnje;
g: ram vrata map (Address => naslov, CLK => CLK, data => data0, CS => en, WE => WE, OE => OE);
end Behavioral;
-------- to je oven
library IEEE;
uporaba IEEE.std_logic_1164.all;
uporaba IEEE.std_logic_unsigned.all;
- ram256x16
Podjetje je ram
pristanišče (Naslov: INTEGER v razponu od 0 do 255;
Podatki: InOut std_logic_vector (15 downto 0);
CS, WE, OE: v std_logic;
CLK: v std_logic
);
Zato podjetje ram;
arhitektura RTL of ram je
Tip ram_array je array (0 do 255) za std_logic_vector (15 downto 0);
signal mem: ram_array;začeti
- P0: proces (CS, WE, OE, Data) je
- tip ram_array je array (0 do 255) za std_logic_vector (15 downto 0);
- spremenljivka mem: ram_array;
set_array: proces (CS, CLK) jekonstanta prog: ram_array: = (
16 => "1000000000000000", 32 => "1000000000000000", 48 => "1000000000000000", 64 => "1000000000000000", 80 => "1000000000000000", 96 => "1000000000000000"
112 => "1000000000000000", 128 => "1000000000000000", 144 => "1000000000000000", 160 => "1000000000000000", 176 => "1000000000000000", 192 => "1000000000000000"
208 => "1000000000000000", 224 => "1000000000000000", 240 => "1000000000000000", drugi => (drugi => '0 '));
začeti
če CS = '0 'then
če falling_edge (CLK) potem
mem <= prog;
end if;
end if;
koncu procesa set_array;read_mem: proces (naslov, OE)
začeti
če OE = '0 'then
Podatki <= mem (naslov);
še
Podatki <= (drugi => 'Z');
end if;
koncu procesa read_mem;
write_mem: proces (naslov, WE)
začeti
če WE = '0 'then
mem (Naslov) <= data;
end if;
koncu procesa write_mem;end architecture RTL;